1. Field of the Invention
This invention is in the field of integrated circuit manufacture. Embodiments of this invention are more specifically directed to methods of forming metal-bearing structures having low defect density due to organometallic polymer and other residues.
2. Description of the Related Art
In recent years, the variety of materials used in the formation of integrated circuits has broadened, so as to take advantage of the properties of certain materials in the continued improvement of device performance and the continued reduction in “chip” area required for realization of a circuit function. The presence of a number of different materials tends to complicate the manufacturing process involved in formation of the integrated circuit, particularly from the standpoint of residues and contaminants generated by various materials. A particular source of such residues comes from the chemical removal, in whole or in part, using “dry” etches (e.g., plasma-assisted processes) or “wet” (liquid-phase) etches of the various layers involved in manufacturing the integrated circuit. The difficulty of removing such residues is increasing, as physical feature sizes are reduced, and as metal-bearing materials such as refractory metals and their compounds are introduced for new functions including making integrated passive components such as capacitors and resistors as well as interconnects.
By way of example to illustrate some of the types of residues that can form during a conventional integrated circuit manufacturing process, FIG. 1 shows a schematic cross-section of an integrated circuit parallel-plate capacitor 100 at a stage during its manufacture according to a conventional process. Referring to FIG. 1, isolation dielectric 6 may be disposed at a surface of substrate 2, which is a semiconductor body at a surface of a wafer at which an integrated circuit is to be formed. As known in the art, isolation dielectric 6 at the surface of substrate 2 serves to electrically isolate various doped regions (e.g., wells, heavily-doped regions such as source and drain regions, and collector and base regions) that are formed at the surface of substrate 2 and serve as part of the circuit being formed. These doped regions are thus present within substrate 2, but are not shown in the cross-sectional views of FIG. 1, either for the sake of clarity, or because such regions are located elsewhere in the device away from the section illustrated in FIG. 1. Polycrystalline silicon (polysilicon) elements 4a, 4b, are formed and patterned at the surface of isolation dielectric 6. In this example, polysilicon element 4a will constitute a lower plate of a planar capacitor, and polysilicon elements 4b constitute conductors in the integrated circuit, connecting various devices. At locations of the integrated circuit other than that shown in FIG. 1, polysilicon elements 4b that overlie a thin gate dielectric layer rather than isolation dielectric 6 may constitute gate electrodes of metal-oxide-semiconductor (MOS) transistors.
Capacitor dielectric 8 is formed of an insulative material, such as silicon nitride or silicon oxide, in a layer over polysilicon elements 4 and isolation dielectric 6, and conductor layer 10 is formed over capacitor dielectric 8. Conductor layer 10 in this example is formed of a metal-bearing material such as a metal, metal alloy, or metal compound, for example aluminum, copper, copper-doped aluminum, tungsten, tantalum, titanium, or conductive compounds of metals such as nitrides or silicides of metals, such as tantalum nitride (TaN). In this example, at the stage of manufacture illustrated in FIG. 1, conductor layer 10 has been photolithographically patterned and etched to define a top plate of the planar capacitor having polysilicon element 4a as its lower plate, with a film of capacitor dielectric 8 between these two plates. As such, a hard mask layer (not shown), for example formed of silicon nitride, was formed over conductor layer 10, and photoresist (not shown) applied over the hard mask layer. In the state of manufacture illustrated in FIG. 1, photoresist has been patterned (selectively exposed and developed) to no longer protect portions of the hard mask layer, the hard mask layer has been etched, using, for example a plasma etch (“dry etch”) to result in a patterned hard mask layer, and the patterned photoresist used for the hard mask etch has been removed. The removal of photoresist may be done in a conventional manufacturing process after the hard mask etch using, e.g., a plasma ash process. Finally, the conductor layer 10 that was unprotected by the hard mask has been etched, for example, by using a wet etch process, and the remaining hard mask layer has been removed.
As known in the art, residues 15x may form as a result of these conventional process steps in several ways. Residues can remain at the surface of the structure after one or more steps, and may be in the form of a contiguous film, or as lines or particles or spots of contaminant material. As one example, during the hard mask etch, due to imperfect selectivity of the hard mask plasma etch, some of the conductor layer 10 is consumed and some of the removed conductor material reacts with the polymer of the photoresist during the hard mask etch process to form organometallic polymers having a composition that includes metallic components of the conductor layer. Such organometallic polymers may be resistant to plasma ashing processes used for photoresist removal, and may even harden further due to cross-linking at elevated temperature, such as during the plasma ash. Residues 15x that are caused by organometallic polymer remain at the surface of the structure over capacitor conductor layer 10. These residues 15x can include an organometallic polymer material itself, and may also include material (e.g., material from hard mask or from capacitor dielectric 8) that was undesirably protected from subsequent etches by residue. As shown in FIG. 1, residues 15x can also gather in the space between closely-spaced polysilicon elements 4b. 
As a second example of residue formation in a conventional process, etching of conductor layer 10 can result in redeposition of the conductive metal-bearing material from conductor layer 10, which is particularly difficult to remove from high aspect ratio spaces such as in the space between closely-spaced polysilicon elements 4b. Removal of these metallic conductive defects, sometimes called “stringers,” can be addressed using a longer etch step for the conductor layer 10, which can result in undesirable lateral and vertical dimensional changes to this layer. Remaining metallic defects can also undesirably mask later etch steps. Thus residues 15x can cause electrical failure in the eventual integrated circuit that is fabricated from the structure shown in FIG. 1, for example by causing electrical leakage between polysilicon elements 4b, or by causing an open or resistive contact if a contact or via etched through subsequently-deposited insulator films is at the location of a remaining residue 15x. In any case, the presence of residues 15x at the surface of elements within the fabricated integrated circuit is undesirable, and can cause increased defect density and resultant yield loss.
Conventional ways of removing residues 15x include performing additional etch steps and a variety of liquid-phase cleaning processes. The required etch and clean process times are often long in an attempt to completely remove residues created by previous process steps. Cleaning processes designed to remove one type of residue can make other types of residue more resistant to removal. These additional etch and cleaning process steps are non-value added, because they do not contribute directly to the formation of the desired circuit structures, and instead add time and cost to the fabrication of the integrated circuits. Sometimes specialized equipment is required to perform cleaning or removal processes. Additional cleaning and removal process steps also increase the defect density on the final devices, not only because there are now additional opportunities to introduce contamination, but also because the vigorous etching and cleaning that must be performed to guarantee removal of unwanted residues also further etches and changes the dimensions and shapes of the desired structures. There thus remains a need for improved methods of fabricating metal-bearing structures in which the formation of organometallic and other residues is minimized or eliminated, in which the residues that are formed tend to be of a composition that is readily removed, and that use process steps for residue removal that cause minimal damage to existing device structures.